1. Field of the Invention
The present invention relates to a chip package structure and a chip packaging method, and more particularly to a multi-row flat non-leaded package structure including a chip with centrally disposed pads and a chip packaging method thereof.
2. Description of the Related Art
FIG. 1 demonstrates a conventional quad/dual flat non-leaded (QFN/DFN) chip package structure 6, which comprises a chip 61, a leadframe 62, and a plurality of bonding wires 64. The chip 61 includes a plurality of bond pads 63 disposed in the central region of the active surface of the chip 61. The leadframe 62 includes a die paddle 65 and a plurality of leads 66. The leads 66 are arranged along at least two opposite sides of the die paddle 65. The chip 61 is mounted on the die paddle 65 of the leadframe 62. The bonding wires 64 respectively connect the bond pads 63 of the chip 61 to the leads 66. Because the bond pads 63 are disposed in the central region of the active surface of the chip 61, long bonding wires 64 are needed to connect the bond pads 63 of the chip 61 to the leads 66 of the leadframe 62. However, long bonding wires 64 are unfavorable to signal transmission, and are prone to wire collapse and sweep, and an increase in packaging cost. In addition, due to the space limitations for layout, the number of leads 66 of the leadframe 62 can hardly be increased; hence, it is difficult to fulfill the requirement for high input/output (I/O) density chips.
FIGS. 2A and 2B respectively illustrate a BGA (ball grid array) package 7 and a chip stack BGA package 9. The BGA package 7 includes a chip 72 mounted on an upper surface of a substrate 71. The chip stack BGA package 9 includes chips 72 and 73, which are stacked and mounted on an upper surface of a substrate 75. Each of the substrates 71 and 75 has a central slot 76. The bond pads 77 of the chip 72 are disposed in the central region of the active surface, and are corresponding in position to the central slot 76 when the chip 72 is mounted on the substrate 71 or 75. The bonding wires 74 electrically connect the bond pads 77 of the chip 72 to the lower surface of the substrate 71 or 75 through the central slot 76. In the chip stack BGA package 9, the chip 73 is fixed onto the chip 72, and the bonding wires are then formed to electrically connect the chip 73 to the upper surface of the substrate 75. Generally, compared with leadframes, the substrates 71 and 75 of the BGA package 7 and the chip stack BGA package 9 which are printed circuit boards are more expensive, resulting in higher cost of the packages 7 and 9. In particular, the substrate 75 of the chip stack BGA package 9 should be a two-layer copper substrate, which is even more expensive. Consequently, such BGA packages suffer from a cost disadvantage in the highly competitive semiconductor industry.
Due to the drawbacks of the afore-mentioned conventional chip packages, improved new chip package structures are demanded.